Conference Paper

A technique to reduce the capacitor size in two stage Miller compensated opamp

Abstract

In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.

Attached files

Authors

Nagulapalli, Rajasekhar
Hayatleh, Khaled
Barker, Steve
Zourob, Saddam
Yassine, Nabil
Naresh Kumar Reddy , B.

Oxford Brookes departments

Faculty of Technology, Design and Environment\School of Engineering, Computing and Mathematics

Dates

Year of publication: 2018
Date of RADAR deposit: 2018-11-19

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License

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Related resources

This RADAR resource is the Accepted Manuscript of A technique to reduce the capacitor size in two stage Miller compensated opamp