Journal Article

A High Performance Single Cycle Memristive Multifunction Logic Architecture


We present a low complexity high performance memristive multifunction logic architecture for low power high frequency operations in a single cycle, which does not require additional control input/logic and multicycle setup/operation. It can be seamlessly integrated with the existing CMOS technology with just 1T-4M design and without additional overhead. Our technique can realise both XOR/AND or XNOR/OR operations simultaneously. Experimental results show that our technique significantly outperforms both CMOS and existing hybrid memristor-CMOS based designs in terms of chip area, power consumptions, and reliable performance especially at high frequencies. With the help of full adder designs, we also demonstrate that the multifunctionality of our architecture can result in highly compact designs.

Attached files


Yang, X
Adeyemo, A
Jabir, A
Matthew, J

Oxford Brookes departments

Faculty of Technology, Design and Environment\Department of Computing and Communication Technologies


Year of publication: 2016
Date of RADAR deposit: 2016-04-07

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