Conference Paper


High performance circuit techniques for neural front-end design in 65nm CMOS

Abstract

Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area.

Attached files

Authors

Nagulapalli, Rajasekhar
Hayatleh, Khaled
Barker, Steve
Zourob, Saddam
Yassine, Nabil
Naresh Kumar Reddy , B.

Oxford Brookes departments

Faculty of Technology, Design and Environment\School of Engineering, Computing and Mathematics

Dates

Year of publication: 2018
Date of RADAR deposit: 2018-11-19


Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License


Related resources

This RADAR resource is the Accepted Manuscript of High performance circuit techniques for neural front-end design in 65nm CMOS

Details

  • Owner: Joseph Ripp
  • Collection: Outputs
  • Version: 1 (show all)
  • Status: Live