Conference Paper


Parasitic effects on memristive logic architecture

Abstract

The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated that our specific memristive logic structure can almost eliminate those effects which are generated by the parasitic components of the memristor. In addition, the propagation delay and the variation of the memristive XOR gate are increased because of the parasitic components. With the delay analysis on cascaded memristive logic design, the experimental results show that our 3T-4M memristive XOR architecture can build the more robust delay based memristive physical unclonable function (PUF) comparing to the existing memristive PUF.

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Authors

Yang, Xiaohan
Adeyemo, Adedotun
Bala, Anu
Jabir, Abusaleh

Oxford Brookes departments

Faculty of Technology, Design and Environment\Department of Computing and Communication Technologies

Dates

Year of publication: 2017
Date of RADAR deposit: 2017-10-31


Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License


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