Journal Article


Minimising impact of wire resistance in low-power crossbar array write scheme

Abstract

This paper presents a circuit level analysis of write operation in memristor crossbar memory array with and without line resistance. Three write schemes: floating line, V/2 and V/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. To solve this problem, we propose a voltage compensating technique for write voltage degradation caused by line resistance during write operation on crossbar array. This technique is able to enhance write voltage in the presence of worst case line resistance and thus enable the design of higher density and reliable crossbar array.

Attached files

Authors

Adeyemo, Adedotun
Jabir, Abusaleh
Mathew, Jimson

Oxford Brookes departments

Faculty of Technology, Design and Environment\Department of Computing and Communication Technologies

Dates

Year of publication: 2017
Date of RADAR deposit: 2017-10-31



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